New lace and arsenic: adventures in weak memory with a program logic (v2)

Bornat, Richard ORCID logoORCID:, Alglave, Jade and Parkinson, Matthew (2016) New lace and arsenic: adventures in weak memory with a program logic (v2). arXiv, [Other] (doi:10.48550/arXiv.1512.01416)

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We describe a program logic for weak memory (also known as relaxed memory). The logic is based on Hoare logic within a thread, and rely/guarantee between threads. It is presented via examples, giving proofs of many weak-memory litmus tests. It extends to coherence but not yet to synchronised assignment (compare-and-swap, load-logical/store-conditional). It deals with conditionals and loops but not yet arrays or heap.

The logic uses a version of Hoare logic within threads, and a version of rely/guarantee between threads, with five stability rules to handle various kinds of parallelism (external, internal, propagation-free and two kinds of in-flight parallelism). There are B and U modalities to handle propagation, and temporal modalities since, Sofar and Ouat to deal with global coherence (SC per location).

The logic is presented by example. Proofs and unproofs of about thirty weak-memory examples, including many litmus tests in various guises, are dealt with in detail. There is a proof of a version of the token ring.

Item Type: Other
Additional Information: Cite as: arXiv:1512.01416v2 [cs.LO]
Research Areas: A. > School of Science and Technology > Computer Science > Foundations of Computing group
Item ID: 28635
Notes on copyright: copyright = perpetual, non-exclusive license
Useful Links:
Depositing User: Professor Richard Bornat
Date Deposited: 19 Dec 2019 16:08
Last Modified: 02 Feb 2023 17:40

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