Parallelised max-Log-Map model
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Official URL: http://dx.doi.org/10.1049/el:20020663
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A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.
|Research Areas:||School of Science and Technology > Computer and Communications Engineering|
School of Science and Technology > Science & Technology
|Deposited On:||03 May 2011 13:51|
|Last Modified:||13 May 2014 15:38|
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