Parallelised max-Log-Map model
Full text is not in this repository.
Official URL: http://dx.doi.org/10.1049/el:20020663
This item is available in the Library Catalogue
A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.
|Research Areas:||A. Middlesex University Schools and Centres > School of Science and Technology > Computer and Communications Engineering|
A. Middlesex University Schools and Centres > School of Science and Technology > Computer Science > SensoLab group
|Deposited On:||03 May 2011 13:51|
|Last Modified:||31 Oct 2014 17:15|
Repository staff only: item control page
Full text downloads (NB count will be zero if no full text documents are attached to the record)
Downloads per month over the past year