Parallelised max-Log-Map model
Full text is not in this repository.
A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.
|Research Areas:||A. > School of Science and Technology > Computer Science > SensoLab group
A. > School of Science and Technology > Computer and Communications Engineering
|Depositing User:||Jonathan Loo|
|Date Deposited:||03 May 2011 13:51|
|Last Modified:||13 Oct 2016 14:23|
Actions (login required)