Parallelised max-Log-Map model

Loo, Jonathan and Salman, K. and Alukaidey, T. and Jimaa, S. A. (2002) Parallelised max-Log-Map model. Electronics Letters, 38 (17). pp. 971-972. ISSN 0013-5194

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Official URL: http://dx.doi.org/10.1049/el:20020663

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Abstract

A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.

Item Type:Article
Research Areas:Science & Technology > Science & Technology
Science & Technology > Algorithms, Architecture & Networks
ID Code:7830
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Deposited On:03 May 2011 13:51
Last Modified:10 Apr 2014 07:31

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