Implementation of non-pipelined and pipelined data encryption standard (DES) using Xilinx Virtex-6 FPGA technology.
Ever, Enver and Taherkhani, Saeid and Gemikonakli, Orhan (2010) Implementation of non-pipelined and pipelined data encryption standard (DES) using Xilinx Virtex-6 FPGA technology. In: CIT2010: 10th IEEE International Conference on Computer and Information Technology. IEEE, pp. 1257-1262. ISBN 9781424475476
Full text is not in this repository.
Data encryption process can easily be quite
complicated and usually requires significant computation
time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation, Virtex-6 Field Programmable Gate Array technology. Finite state machine is used only in non-pipelined implementation, and it is not implemented for the pipelined approach. The testing of the implemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. When pipelined approach is employed on the other hand, 17 clock signals are required for the initial phase only, and one clock signal is sufficient afterwards for each data generation cycle. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to program the design.
|Item Type:||Book Section|
|Additional Information:||Conference held in Bradford, West Yorkshire, UK June 29-July 01, 2010.|
|Research Areas:||A. > School of Science and Technology > Computer and Communications Engineering
A. > School of Science and Technology > Computer Science > SensoLab group
|Depositing User:||Dr. Enver Ever|
|Date Deposited:||01 Feb 2011 10:19|
|Last Modified:||13 Oct 2016 14:22|
Actions (login required)